1. Technical Field
The invention relates to semiconductor manufacturing and, more particularly, to the formation of a dual damascene structure.
2. Background of Related Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit. Integrated circuits can be useful for computers and electronic equipment and may contain millions of transistors and other circuit elements that can be fabricated on a single silicon crystal semiconductor device, i.e., chip. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device becomes more difficult as the complexity of the integrated circuit is increased. Thus, multi-level or multi-layered schemes known as dual damascene structures are desirable due to their ability to increase the device's density and, therefore, allow stacked interconnected levels of a densely packed semiconductor device.
When fabricating integrated circuits with a dual damascene structure, an insulating or dielectric material such as silicon oxide of a semiconductor device will normally be patterned with, for example, several thousand openings to create conductive line openings and via openings. The conductive line and via openings can then be filled with a conductive metal layer, e.g., aluminum, to interconnect the active and/or passive elements of the integrated circuits. The dual damascene structure may also be used for forming multilevel conductive lines of metal, e.g., copper, in insulating layers, e.g., polyimide, of multi-layer substrates on which semiconductor devices can be mounted.
Methods for manufacturing a dual damascene structure are known. See, e.g., U.S. Pat. Nos. 5,422,309; 5,529,953; 5,602,423; and 5,614,765. Generally, a standard dual damascene structure can be manufactured by first coating an insulating layer with a antireflective coating (ARC) and photoresist layers. The photoresist is then exposed through a first mask with an image pattern of via openings and the pattern can be anisotropically etched through insulating layer to expose the underlying conductive layer. After etching the via openings, the remaining ARC and photoresist are removed. New layers of ARC and photoresist are then deposited. The resist is exposed through a second mask with an image pattern of the conductive line openings. The second image pattern will typically be aligned with the first mask pattern to encompass the via openings with the conductive line openings. The portions of the resist where the conductive line openings are to be formed are removed, exposing the via opening and insulating layer. The exposed insulating layer is then etched to a desired depth equal to the height of the conductive line. When the etching is complete, both the via openings and the conductive line openings may be filled with a conductive metal layer.
The second deposition of ARC and photoresist layers fills the vias with ARC, causing polymer to build-up in the vias during the subsequent etch that forms the conductive line openings. As groundrules become smaller and smaller, such polymer build-up leads the formation of SiO.sub.2 fences at the interface of the via and conductive line openings. The presence of fences disrupts the flow of metal into the vias, causing voids to form therein. Such voids result in increase via resistance and, in some cases, via failures.
From the above discussion, there is a need to provide a dual damascene structure without the formation of fences at the via-line openings.